The IC design is increasingly complex and the cycle, for which ICs are put to the market, is needed to be increasingly shorter, thus it is needed for the developers to shorten the cycle, for which chips are put to the market, as much as possible while ensuring the quality.
At present, for different project requirements, different design techniques and design tools, requirements for Design for Testability (DFT) of a full chip are different. As a result, in the phase of circuit behaviour level description (RTL) design, different DFT design requirements need to be introduced to different modules, design codes and code hierarchies, and different DFT design requirements (such as a testable control interface of a storage unit, a low-power control interface and a functional test interface) will require to add different DFT design entities to RTL codes. Such design entities usually pass through multiple hierarchies and modules of codes of the full chip, and after the modules and hierarchies change, DFT design entities need to be updated, modified and added again, which requires designers and integrators to make sufficient communication and exchanges to confirm and analyse signals. Due to differences in individual understanding and signal naming, errors are difficult to be avoided, resulting in the iterative construction and release of a version and thus wasting a lot of human resources. These potential factors shorten the IC development cycle.